Samsung recently hosted the Samsung Foundry Forum 2018 (SFF) in Japan and released several important messages. In addition to reiterating plans to start mass production (HVM) with extreme ultraviolet lithography (EUVL) over the next few quarters, and reiterating plans to use gate FETs (GAAFET) with three nanonodes, Samsung has added new 8LPU technology to its roadmap. In addition, the provision of 3D SiP in 2019 and the risk of producing 3nm nodes in 2020 are also highlights.
10 nm node
The overall roadmap for Samsung’s plant was announced earlier this year, so at SFF in Japan, Samsung reiterated some of its plans and made some amendments, providing additional details about its future plans. First, Samsung added a new process called the low power ultimate based on the 10-nanometer process, which, according to Samsung’s classification, is prepared for the need for high clock frequency and high transistor density SoC. 8LPU is a further upgrade of 8LPP technology platform, which may increase transistor density and increase frequency. Samsung’s 8LPP technology was put into production last year, and based on Samsung’s 10-nm node development, a narrower minimum metal spacing could reduce the area by 10% (the same complexity) and power consumption by 10% (the same frequency and complexity) compared with 10LPP. Samsung, however, did not disclose how it could upgrade the 8LPU on an 8LPP basis, such as design rules, new libraries, and minimum metal spacing.
Samsung’s 8LPP and 8LPU technologies are geared toward customers who need higher performance or lower power or higher transistor density than 10LPC and 10LPU processes can provide, but cannot obtain Samsung’s 7LPP or more advanced manufacturing technology EUVL. Risk production of 8LPU will begin in 2018 and mass production is expected to begin next year at the Fab S1 plant in Giheung, South Korea.
Samsung, a leading manufacturer of chips, has already announced that its 7Nm LPP process will be put into production in the second half of 2008, and it announced 5/4/3nm technology directly at yesterday’s Samsung Foundry Forum.
Among them, 5nm LPE process will further reduce the chip core area and bring lower power consumption compared with 7Nm LPP; 4nm LPE / LPP will be Samsung’s last use of FinFET technology on the chip, improving chip area compression. 3nm GAAE/GAAP uses a new GAA (Gate-All-Around) nanotechnology, which requires a redesign of the transistor underlying structure to overcome the physical and performance limits of current technology, enhance gate control, and greatly improve performance
Post time: Sep-18-2018